ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 183

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.7.2
15.7.3
8077H–AVR–12/09
FDEMASK - Fault Detect Event Mask Register
FDCTRL - Fault Detection Control Register
• Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask
These bits enables the corresponding event channel as fault condition input source. Event from
all event channels will be ORed together allowing multiple sources to be used for fault detection
at the same time. When a fault is detected the Fault Detect Flag FDF is set and the fault detect
action (FDACT) will be performed.
• Bit 7:5 - RES - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and the fault protection is enabled, and OCD break request is
treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition.
• Bit 3 - RES - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2- FDMODE: Fault Detection Restart Mode
This bit sets the fault protection restart mode. When this bit is cleared Latched Mode is use, and
when this is set Cycle-by-Cycle Mode is used.
In Latched Mode the waveform output will remain in the fault state until the fault condition is no
longer active and the FDF has been cleared by software. When both of these conditions are
met, the waveform output will return to normal operation at the next UPDATE condition.
In Cycle-by-Cycle Mode the waveform output will remain in the fault state until the fault condition
is no longer active. When this condition is met, the waveform output will return to normal opera-
tion at the next UPDATE condition
• Bit 1:0 - FDACT[1:0]: Fault Detection Action
These bits define the action performed if a fault condition is detected, according to
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
R/W
R
7
0
-
7
0
R/W
R
6
0
-
6
0
R/W
R
5
0
-
5
0
.
FDDBD
R/W
R/W
4
0
FDEVMASK[7:0]
4
0
R/W
R
3
0
-
3
0
FDMODE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
FDACT[1:0]
XMEGA A
R/W
R/W
0
0
0
0
Table
FDEMASK
FDCTRL
15-1.
183