MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 8

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Industrial Temperature
General Notes
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
The 512Mb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs
allows for concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
The industrial temperature (IT) device has two simultaneous requirements: ambient
temperature surrounding the device cannot exceed –40°C or +85°C, and the case
temperature cannot exceed –40°C or 95°C. JEDEC specifications require the refresh rate
to double when T
refresh option. Additionally, ODT resistance and the input/output impedance must be
derated when the T
• The functionality and the timing specifications discussed in this data sheet are for the
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
• Complete functionality is described throughout the document, and any page or
• Any specific requirement takes precedence over a general statement.
DLL-enabled mode of operation.
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into 2 bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
C
exceeds 85°C; this also requires use of the high-temperature self
C
is < 0°C or > 85°C.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
General Description
©2004 Micron Technology, Inc. All rights reserved.