MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 74

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ODT Timing
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Once a 12ns delay (
enabled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate in either synchronous mode or asynchronous mode,
depending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 56 on page 75.
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]),
Figure 58 on page 76 and Table 12 on page 76.
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
t
and Table 13 on page 77.
ODT turn-off timing, prior to entering any power-down mode, is determined by the
parameter
signal satisfies
(MIN) is satisfied,
shows the example where
until state T3. When
ODT turn-on timing prior to entering any power-down mode is determined by the
parameter
satisfies
satisfied,
where
t
ODT turn-off timing after exiting any power-down mode is determined by the parameter
t
fies
fied,
t
not satisfied,
ODT turn-on timing after exiting either slow-exit power-down mode or precharge
power-down mode is determined by the parameter
on page 81. At state Ta1, the ODT HIGH signal satisfies
down mode at state T1. When
eters apply. Figure 63 also shows the example where
ODT HIGH occurs at state Ta0. When
parameters apply.
AONPD and
ANPD (MIN) is not satisfied,
AXPD (MIN), as shown in Figure 62 on page 80. At state Ta1, the ODT LOW signal satis-
AXPD (MIN) is not satisfied since ODT LOW occurs at state Ta0. When
t
AXPD (MIN) after exiting power-down mode at state T1. When
t
AOFD and
t
ANPD (MIN) is not satisfied since ODT HIGH does not occur until state T3. When
t
ANPD (MIN) prior to entering power-down mode at T5. When
t
AOND and
t
t
ANPD (MIN), as shown in Figure 60 on page 78. At state T2, the ODT HIGH
ANPD, as shown in Figure 61 on page 79. At state T2, the ODT HIGH signal
t
AOND,
t
t
AOFPD timing parameters are applied, as shown in Figure 59 on page 77
AOFPD timing parameters apply.
t
ANPD (MIN) prior to entering power-down mode at T5. When
t
AOF timing parameters apply. Figure 62 also shows the example where
t
AOFD and
t
MOD) has been satisfied, and after the ODT function has been
t
t
AON,
ANPD (MIN) is not satisfied,
t
AON timing parameters apply. Figure 61 also shows the example
t
ANPD (MIN) is not satisfied since ODT HIGH does not occur
t
AOFD, and
t
74
t
AONPD timing parameters apply.
t
AOF timing parameters apply. Figure 60 on page 78 also
AXPD (MIN) is satisfied,
t
AXPD (MIN) is not satisfied,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
AOF timing parameters are applied, as shown in
512Mb: x4, x8, x16 DDR2 SDRAM
t
AOFPD timing parameters apply.
t
AXPD (MIN), as shown in Figure 63
t
AXPD (MIN) is not satisfied since
t
t
AXPD (MIN) after exiting power-
AOND and
©2004 Micron Technology, Inc. All rights reserved.
t
t
t
AONPD timing
AXPD (MIN) is satis-
AON timing param-
t
t
AXPD (MIN) is
ANPD (MIN) is
ODT Timing
t
ANPD