MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 114

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 45:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Parameter/Condition
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating;
Data bus inputs are floating
Operating bank interleave read current: All bank
interleaving reads, I
AL =
t
HIGH, CS# is HIGH between valid commands; Address
bus inputs are stable during deselects; Data bus
inputs are switching (see Table 47 on page 115 for
details)
RC (I
t
DD
RCD (I
),
t
RRD =
DD
DDR2 I
Notes: 1–7; notes appear on page 114
) - 1 x
t
RRD (I
Notes:
OUT
t
CK (I
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
Specifications and Conditions (continued)
),
t
);
1. I
2. Input slew rate is specified by AC parametric test conditions (Table 46 on page 115).
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
5. Definitions for I
6. I
7. The following I
RCD =
t
CK =
V
–37V V
I
LOW
HIGH
Stable
Floating
Switching
Switching
outside of the range 0°C ≤ T
When
T
When
T
DD
DD
DD
DD
C
C
DD
≤ 0°C
≥ 85°C
1, I
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
values must be met with all combinations of EMR bits 10 and 11.
t
t
RCD (I
= +1.8V ±0.1V, V
CK (I
DD
DD
4R, and I
Q = +1.9V ±0.1V, V
DD
DD
I
derated by 2 percent; and I
I
derated by 2 percent; I
derated by 30 percent; and I
increase by this amount if T
),
DD
DD
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
Inputs changing between HIGH and LOW every other clock cycle (once per two
clocks) for address and control signals
Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
); CKE is
t
IN
IN
RC =
DD
2P and I
0, I
DD
≤ V
≥ V
DD
DD
s must be derated (I
DD
conditions:
),
IL
IH
7 require A12 in EMR1 to be enabled during testing.
1, I
DD
(
(
AC
AC
DD
Q = +1.8V ±0.1V, V
I
DD
Sym
REF
I
I
) MAX
DD
) MIN
DD
DD
3P (slow) must be derated by 4 percent; I
2N, I
6L
6
7
= V
114
DD
C
≤ 85°C:
L = +1.9V ±0.1.
DD
DD
x4, x8, x16
Q/2
2Q, I
Config
x4, x8
DD
x16
DD
2P must be derated by 20 percent; I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
C
limits increase) on IT-option devices when operated
3N, I
DD
< 85°C and the 2x refresh option is still enabled)
6 and I
DD
6 must be derated by 80 percent (I
L = +1.8V ±0.1V, V
I
DD
DD
512Mb: x4, x8, x16 DDR2 SDRAM
-25E
300
370
3P (fast), I
7
3
DD
Specifications and Conditions
7 must be derated by 7 percent
300
370
-25
7
3
DD
4R, I
240
350
-3E
7
3
REF
©2004 Micron Technology, Inc. All rights reserved.
DD
= V
DD
4W, and I
240
340
-3
7
3
4R and I
DD
Q/2.
-37E
DD
225
340
C
7
3
3Pslow must be
≤ +85°C.
DD
DD
DD
5W must be
5W must be
340
6 will
-5E Units
220
7
3
mA
mA