MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 24

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10:
DLL Enable/Disable
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Extended Mode Register Definition
Notes:
1. During initialization, all three bits must be set to “1” for OCD default state, then must be
2. E13 (A13) is not used on the x16 configuration.
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 10. The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before
a READ command can be issued, to allow time for the internal clock to synchronize with
the external clock. Failing to wait for synchronization to occur may result in a violation
of the
E15
0
0
1
1
set to “0” before initialization is finished, as detailed in the notes on pages 17–18.
BA1
E14
15
MRS
0
1
0
1
E12
0
1
t
14
AC or
BA0
Extended mode register (EMRS2)
Extended mode register (EMRS3)
E9
Extended mode register (EMRS)
0
0
0
1
1
E11
0
1
Disabled
Outputs
Enabled
0
13
E8
Mode register set (MRS)
A13
2
RDQS Enable
0
0
1
0
1
E10
0
1
out
Mode Register Set
E7
12
0
1
0
0
1
Yes
A12 A11
No
t
DQS# Enable
DQSCK parameters.
RDQS
Disable
Enable
OCD Operation
OCD not supported
Reserved
Reserved
Reserved
OCD default state
11
DQS#
10
A10
OCD Program
9
A9
E6
0
0
1
1
8
A8
1
E2
0
1
0
1
1
7
A7 A6 A5 A4 A3
Rtt (nominal)
R
R
TT
24
150Ω
75Ω
TT
50Ω
6
disabled
Posted CAS#
5
E5
0
0
0
0
1
1
1
1
4
E4
0
0
1
1
0
0
1
1
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
E3
0
1
0
1
0
1
0
1
R
TT
2
Posted CAS# Additive Latency (AL)
A2
ODS
E1
0
1
1
512Mb: x4, x8, x16 DDR2 SDRAM
A1 A0
Full strength (18Ω target)
Reduced strength (40Ω target)
DLL
E0
0
1
0
Output Drive Strength
Disable (Test/Debug)
Reserved
Reserved
Reserved
Enable (Normal)
Extended Mode
Register (Ex)
Address Bus
0
1
2
3
4
DLL Enable
©2004 Micron Technology, Inc. All rights reserved.
DLL Enable/Disable