MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 71

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Precharge Power-Down Clock Frequency Change
Figure 54:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
COMMAND
DQS, DQS#
ADDR
ODT
CK#
CKE
DM
DQ
CK
High-Z
High-Z
VALID 1
VALID
T0
Input Clock Frequency Change During Precharge Power-Down Mode
t CH
power-down mode
t CK
Notes:
Enter precharge
PREVIOUS CLOCK FREQUENCY
t CL
NOP
T1
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequen-
cies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. Once the input clock frequency is changed,
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via EMR after precharge power-down exit. Depending on
the new clock frequency, an additional LM command might be required to appropriately
set the WR MR[11, 10, 9]. During the DLL relock period of 200 cycles, ODT must remain
off. After the DLL lock time, the DRAM is ready to operate with a new clock frequency.
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
2. A minimum of 2 x
3. Once the new clock frequency has changed and is stable, a minimum of 1 x
4. Minimum CKE HIGH time is
2 x t CK (MIN) 2
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
clock frequencies.
prior to exiting precharge power-down.
requires a minimum of three clock cycles of registration.
T2
t CKE (MIN) 4
T3
t
Frequency
CK is required after entering precharge power-down prior to changing
change
Precharge Power-Down Clock Frequency Change
Ta0
t
1 x t CK (MIN) 3
CKE = 3 x
71
t CH
power-down mode
t CK
Exit precharge
t CL
NOP
Ta1
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK. Minimum CKE LOW time is
NEW CLOCK FREQUENCY
512Mb: x4, x8, x16 DDR2 SDRAM
NOP
Ta2
t XP
t CKE (MIN) 4
DLL RESET
Indicates a break in
time scale
Ta3
LM
©2004 Micron Technology, Inc. All rights reserved.
200 x t CK
t
NOP
CKE = 3 x
Ta4
t
CK is required
DON’T CARE
t
VALID
VALID
CK. This
Tb0