MT46V64M8P-6T:F Micron Technology Inc, MT46V64M8P-6T:F Datasheet
MT46V64M8P-6T:F
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MT46V64M8P-6T:F Summary of contents
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Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg banks MT46V64M8 – 16 Meg banks MT46V32M16 – 8 Meg banks Features • +2.5V ±0.2V ...
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Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) 1 Yes -5B – -6 – -6T – -75E ...
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Table of Contents State Diagram ...
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State Diagram Figure 2: Simplified State Diagram Power applied Note: This diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. N; Core DDR ...
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... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock (CK and CK#) ...
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Automotive Tempature The automotive temperature (AT) option adheres to the following specifications: • 16ms refresh rate • Self refresh not supported • Ambient and case temperatures cannot be less than –40°C or greater than +105°C PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - ...
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... Functional Block Diagrams The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a 4-bank DRAM. Figure 3: 128 Meg x 4 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTERS COUNTER 15 13 A0–A12, ADDRESS ...
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... GENERATOR COL0 INPUT 16 REGISTERS 1 1 MASK 1 1 WRITE 16 2 FIFO & DRIVERS Out In DATA CK COL0 BANK3 BANK2 BANK1 BANK0 MEMORY ARRAY DATA READ MUX LATCH 16 2 DQS 16384 GENERATOR COL0 INPUT 32 REGISTERS 2 2 MASK 2 2 WRITE 4 32 512 FIFO (x32) & ...
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Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignment (Top View DQ0 DQ1 ...
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Figure 7: 60-Ball FBGA Ball Assignment (Top View REF REF DQ14 DQ12 DQ10 DQ8 V REF PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D2.fm - ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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Table 4: Pin and Ball Descriptions (continued) FBGA TSOP Numbers Numbers Symbol E3 51 DQS E7 16 LDQS E3 51 UDQS V F8 B2, D2, C8 15, 55, DD E8, ...
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Package Dimensions Figure 8: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold ...
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Figure 9: 60-Ball FBGA (10mm x 12.5mm) 0.85 ±0.05 SEATING PLANE C 0.10 C .45 60X Ø 0.80 (TYP) SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40. BALL A9 11.00 5.50 ±0.05 3.20 ±0.05 ...
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Electrical Specifications – I Table 6: I Specifications and Conditions (x4, x8 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 8 ...
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Table 7: I Specifications and Conditions (x16 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 8 on page 17 A Parameter/Condition ...
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Table 8: I Test Cycle Times DD Values reflect number of clock cycles for each test Speed Clock Cycle I Test Grade Time -75/75Z 7.5ns DD -75E 7.5ns -6/-6T 6ns -5B 5ns I 1 -75 7.5ns DD ...
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Electrical Specifications – DC and AC Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above ...
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Table 11: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) Notes: 1–5, 17 apply to the entire table; Notes appear on page 35; V Parameter/Condition Supply voltage I/O supply voltage I/O reference voltage I/O termination voltage (system) ...
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Figure 10: Input Voltage Waveform Transmitter Notes Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR ...
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Table 13: Clock Input Operating Conditions Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Parameter/Condition Clock input mid-point voltage: CK and CK# Clock input voltage ...
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Table 14: Capacitance (x4, x8 TSOP) Note: 14 applies to the entire table; Notes appear on page 35 Parameter Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQ, ...
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Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) (continued) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Write recovery time Internal ...
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Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
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Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
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Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...
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Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output ...
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The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 17. Inputs are not recognized as valid until ...
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The input capacitance per pin group will not differ by more than this maximum amount for any given device. 31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). Figure 12: Derating Data ...
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The full driver pull-up current variation from MIN to MAX process; temperature 38d. The driver pull-up current variation within nominal limits of voltage and temper- 38e. The full ratio variation of MAX to MIN pull-up and pull-down current should ...
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The driver pull-up current variation, within nominal voltage and temperature 39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should 39f. The full ratio variation of the nominal pull-up to pull-down current should be Figure 15: ...
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RPST end point and but specify when the device output is no longer driving ( t ( RPRE). 45. During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the ...
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Table 26: Normal Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 ...
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Table 27: Reduced Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 ...
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Commands Tables 28 and 29 provide a quick reference of available commands. Two additional Truth Tables—Table 30 on page 44 and Table 31 on page 45—provide current state/next state information. Table 28: Truth Table 1 – Commands CKE is HIGH ...
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Table 30: Truth Table 3 – Current State Bank n – Command to Bank n Notes: 1–6 apply to the entire table; Notes appear below Current State CS# RAS# CAS# Any Idle L L Row active L ...
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Refreshing: Starts with registration of an AUTO REFRESH command and ends when • Accessing mode register: Starts with registration of an LMR command and ends when • Precharging all: Starts with registration of a PRECHARGE ALL command and ends ...
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This table describes alternate bank operation, except where noted (that is, the current state is for bank n, and the commands shown are those allowed to be issued to bank m, assuming that bank such a ...
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Table 33: Truth Table 5 – CKE Notes 1–6 apply to the entire table; Notes appear below CKE CKE Current State n Power-down Self refresh L H Power-down Self refresh H L All banks idle Bank(s) active ...
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ACTIVE (ACT) The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in Figure 17. The value on the BA0, BA1 inputs selects ...
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READ The READ command is used to initiate a burst read access to an active row, as shown in Figure 18 on page 49. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs ...
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WRITE The WRITE command is used to initiate a burst write access to an active row as shown in Figure 19. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai and configuration, ...
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PRECHARGE (PRE) The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks as shown in Figure 20. The value on the BA0, BA1 inputs selects the bank, and the ...
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Operations INITIALIZATION Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described ...
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Figure 21: INITIALIZATION Flow Diagram Step PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B ...
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Figure 22: INITIALIZATION Timing Diagram ( ( ) ) VTD REF ) ) ( ( CK ...
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... A8, which is self- clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation ...
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Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 23 on page 55. The burst length determines the maximum ...
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CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set (-5B only) ...
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Table 35: CAS Latency Speed -5B -6/-6T -75E -75Z -75 Operating Mode The normal operating mode is selected by issuing an LMR command with bits A7–An each set to zero and bits A0–A6 set to the desired values. A DLL ...
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Figure 25: Extended Mode Register Definition Notes the most significant row address bit from Table 2 on page 2. 2. The QFC# option is not supported. ACTIVE After a row ...
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Figure 26: Example: Meeting T0 T1 CK# CK Command ACT NOP Row Address Bank x BA0, BA1 READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, ...
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Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 31 on page 66. The BURST TERMINATE latency is equal to the CL, that is, the BURST TERMINATE command should be issued x ...
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Figure 27: READ Burst T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ ...
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Figure 28: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
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Figure 29: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
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Figure 30: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
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Figure 31: Terminating a READ Burst T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n ...
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Figure 32: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS CK# CK READ Command Bank a, Address Col n DQS DQ DM ...
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Figure 33: READ-to-PRECHARGE T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ Notes: ...
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Figure 34: Bank READ – Without Auto Precharge CKE Command NOP ACT Row Address A10 Row BA0, ...
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Figure 35: x4, x8 Data Output Timing – DQ (first data no longer valid) DQ (first data no longer valid) All DQ and DQS collectively t Notes the lesser DQSQ is derived at each ...
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Figure 36: x16 Data Output Timing – CK# CK LDQS (last data valid (first data no longer valid (last data valid) ...
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... WRITE burst (after selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...
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Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of ...
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Figure 38: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...
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Figure 39: Consecutive WRITE-to-WRITE T0 CK# CK WRITE Command Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are ...
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Figure 40: Nonconsecutive WRITE-to-WRITE Command Address t DQSS (NOM) Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following Three ...
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Figure 42: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...
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Figure 43: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...
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Figure 44: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...
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Figure 45: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...
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Figure 46: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...
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Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...
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Figure 48: Bank WRITE – Without Auto Precharge CKE NOP 1 ACT Command Row Address A10 Row BA0, ...
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Figure 49: WRITE – DM Operation CKE ACT NOP Command Row Address A10 Row BA0, BA1 Bank ...
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Figure 50: Data Input Timing CK# CK DQS DQ DM Notes: 1. WRITE command issued at T0 DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during 4. For x16, LDQS controls the lower byte and ...
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Figure 51: Bank READ – with Auto Precharge CKE ACT NOP Command Address Row A10 Row IS IH BA0, BA1 Bank ...
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Figure 52: Bank WRITE – with Auto Precharge CKE Command NOP ACT Address Row A10 Row BA0, ...
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Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends Figure 53: Auto Refresh Mode ...
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NOPs for 200 additional clock cycles before applying a READ. Any command other than a READ can be performed reset. NOP or DESELECT commands must be issued during the Self refresh is not supported on ...
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Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend ...
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Figure 55: Power-Down Mode CK# CK CKE Command Address DQS DQ DM Notes: 1. Once initialized this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is ...