MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet
MT48H8M32LFB5-75:H
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MT48H8M32LFB5-75:H Summary of contents
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Mobile SDRAM MT48H16M16LF – 4 Meg banks MT48H8M32LF – 2 Meg banks Features • Fully synchronous; all signals registered on positive edge of system clock • 1.70–1.95V DD DDQ ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 256Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Figure 1: 256Mb Mobile SDRAM Part Numbering Example Part Number: MT48H8M32LFB5-75LIT V 1.8V/1.8V General Description The Micron memory containing 268,435,456-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 col- umns by 16 bits. Each of the x32’ ...
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... The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM offers substantial advances in DRAM operating performance, including the abil- ity to synchronously burst data at a high data rate with automatic column-address gen- ...
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... A[11:0], ADDRESS 14 BA[1:0] REGISTER 9 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4096 x 512 x 32) DECODER SENSE AMPLIFIERS 4096 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC ...
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Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 8mm x 9mm PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ DQ15 V SS SSQ DQ14 ...
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Figure 5: 90-Ball VFBGA (Top View) – 8mm x 13mm PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ DQ26 DQ24 ...
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... A[12:0] and READ/WRITE command (column-address A[8:0] (x32); column-address A[8:0] (x16); with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA[1:0]. The address inputs also provide the op-code during a LMR command ...
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Table 3: VFBGA Ball Descriptions (Continued) 54-Ball VFBGA 90-Ball VFBGA A8, B9, B8, C9, R8, N7, R9, N8, C8, D9, D8, E9, P9, M8, M7, L8, E1, D2, D1, C2, L2, M3, M2, P1, C1, B2, B1, A2 N2, R1, ...
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Functional Description In general, a 256Mb SDRAM is quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are ...
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Register Definition Mode Register There are two mode registers in the component: mode register and extended mode reg- ister (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register is used to define the specific ...
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Figure 6: Mode Register Definition M14 M13 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN BA1 BA0 A12 A11 A10 M14 M13 M12 M11 M10 ...
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Table 4: Burst Definition Table Burst Length Starting Column Address Continuous n = A[8:0] ...
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Figure 7: CAS Latency COMMAND COMMAND Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use. Reserved states should not ...
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Figure 8: EMR Definition E14 E13 E12 E11 0 0 – – Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect. The EMR ...
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... Partial-Array Self Refresh (PASR) For further power savings during self refresh, the partial-array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during self refresh. The following refresh options are available. 1. All banks (banks and 3). ...
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Commands Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables appear following “Opera- tions” on page 23. These tables provide current state/next state information. Table 5: ...
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... Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is regis- tered LOW, the corresponding data will be written to memory; if the DQM signal is regis- tered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location ...
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BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or continuous page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in “Operations” on page 23. ...
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... Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power to the memory array. Data will not be retained once the device enters deep power-down mode. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ RP) is completed ...
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Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...
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Figure 10: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 11. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled ...
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Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A continuous page burst will proceed until terminated (at the end of the page, it will wrap to the start address and continue). ...
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Note: Each READ command may be to either bank. DQM is LOW. Figure 13: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be ...
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WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 (as in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would ...
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Figure 15: READ-to-WRITE with Extra Clock Cycle DQM COMMAND ADDRESS Note The READ command may be to any bank, and the WRITE command may be to any bank. Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Note: DQM ...
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Continuous page bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, pro- vided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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Figure 19: WRITE Burst CLK COMMAND ADDRESS Note DQM is LOW. Figure 20: WRITE-to-WRITE CLK COMMAND ADDRESS Note DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst ...
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In the case of a fixed-length burst being executed to completion, a PRECHARGE com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- ...
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Figure 23: WRITE-to-PRECHARGE t t WR@ DQM COMMAND ADDRESS t t WR@ DQM COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 24: Terminating a WRITE Burst COMMAND ...
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Fixed-length or continuous page WRITE bursts can be truncated with the BURST TER- MINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM ...
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... Deep Power-Down Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data in the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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Concurrent Auto Precharge An access command (READ or WRITE second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAM, unless the SDRAM supports concurrent auto precharge. Micron ...
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Figure 28: Clock Suspend During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM is LOW. Figure 29: READ with Auto Precharge Interrupted by a READ COMMAND ...
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Figure 30: READ with Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS Note: DQM is HIGH prevent D WRITE with Auto Precharge 1. Interrupted by a READ (with or without auto ...
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Figure 31: WRITE with Auto Precharge Interrupted by a READ COMMAND BANK n Internal States BANK m ADDRESS Note: DQM is LOW. Figure 32: WRITE with Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS ...
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Truth Tables Table 6: Truth Table – CKE Notes: 1–4 CKE CKE Current State n Power-down Self refresh Clock suspend Deep power-down L H Power-down Deep power-down Self refresh Clock suspend H L All banks idle All ...
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Table 7: Truth Table – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# WE# Command (Action) Any Idle ...
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The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not shown ...
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Table 8: Truth Table – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# WE# Command (Action) Any Idle X X Row activating, ...
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All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
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Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 52 and 53 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width ...
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Table 12: AC Functional Characteristics Notes 9,11 notes appear on page 52 and 53 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
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Table 13: I Specifications and Conditions (x16) DD Notes 11, 13; notes appear on page 52 and 53; V Parameter/Condition Operating current: Active mode READ or WRITE; Standby current: Power-down mode; All banks idle; ...
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Table 14: I Specifications and Conditions (x32) DD Notes 11, 13; notes appear on page 52 and 53; V Parameter/Condition Operating current: Active mode READ or WRITE; Standby current: Power-down mode; All banks idle; ...
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Table 15: I – Self Refresh Current Options DD7 Notes: 2, 28, 30; notes appear on page 52 and page 53 Temperature-Compensated Self Refresh Parameter/Condition Self refresh current: CKE = LOW – 4-bank refresh Self refresh current: CKE = LOW ...
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Table 16: Capacitance Note: 2; notes appear on page 52 and 53 Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQs PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Symbol Min ...
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Notes 1. All voltages referenced This parameter is sampled. V 0.9V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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V IH not be greater than one third of the cycle rate. V width ≤ 3ns. 23. The clock frequency can only be changed during clock stop, power-down, or while in a self-refresh mode. 24. Auto precharge mode only. ...
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Timing Diagrams Figure 34: Initialize and Load Mode Register CLK ( ( ) ) CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ...
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Figure 35: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM ADDR ALL BANKS A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Two clock cycles Precharge all All ...
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Figure 36: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM ADDR COLUMN ...
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Figure 37: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM ADDR ALL BANKS A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Precharge all active banks Notes: ...
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Figure 38: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM ADDR ALL BANKS A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Precharge all active banks PDF:09005aef8219eeeb/Source: ...
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Figure 39: READ – without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ROW ADDR ROW ...
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Figure 40: READ – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 ...
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Figure 41: Single READ – without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 DISABLE AUTO ...
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Figure 42: Single READ – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 t AS ...
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Figure 43: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 t ...
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Figure 44: READ – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM/ DQML, DQMH Address ROW COLUMN ...
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Figure 45: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 DISABLE ...
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Figure 46: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN ...
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Figure 47: WRITE – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN ...
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Figure 48: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 DISABLE AUTO ...
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Figure 49: Single WRITE – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM ROW ADDR ROW ...
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Figure 50: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ROW COLUMN m ADDR ...
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Figure 51: WRITE – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM/ DQML, DQMH Addresss ROW ROW ...
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Figure 52: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ADDR ROW ROW A10 ...
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Package Dimensions Figure 53: 54-Ball VFBGA (8mm x 9mm) SEATING PLANE A 0.10 A 54X Ø0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0. 0.40 SMD BALL PAD. BALL A9 6.40 3.20 ...
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Figure 54: 90-Ball VFBGA (8mm x 13mm) Seating plane A 0 ±0.1 90X 0.45 Dimensions apply to solder balls post- reflow. Pre-reflow balls are Ø0. Ø0.4 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 ...
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... Added “Revision :G” to Figure 1 on page 5. • Changed refresh counter from “12” to “13” and changed Bank0 Memory Array from “8,192” to “4,096” in Figure 3 on page 7. • Changed E2 “DNU” and added the following sentence in the: “TEST pin must be tied to VssQ in normal operation” ...
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Moved Figure 25 to page 34. • Removed the “In order to exit deep power down...” paragraph on page 35. • Replaced text in note 9 and removed “Deep power down” rows in Table 7 on page 41. • ...
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Changed the “8” address lines going into the “column address counter/Latch” to “9” in Figure 2. • Changed all references and changed the “8” address lines going into the “column address counter/Latch” to “9” in ...