MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 52

IC DDR2 SDRAM 512MBIT 5NS 60FBGA

MT47H64M8CB-5E:B

Manufacturer Part Number
MT47H64M8CB-5E:B
Description
IC DDR2 SDRAM 512MBIT 5NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H64M8CB-5E:B

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (64M x 8)
Speed
5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H64M8CB-5E:B
Manufacturer:
MICRON
Quantity:
12 388
Part Number:
MT47H64M8CB-5E:B
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H64M8CB-5E:B TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 32:
Figure 33:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Consecutive WRITE-to-WRITE
Nonconsecutive WRITE-to-WRITE
Notes:
Notes:
t
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within
t
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within
DQSS (NOM)
DQSS (NOM)
COMMAND
DQS, DQS#
COMMAND
DQS, DQS#
ADDRESS
DI b.
DI n.
DI b.
DI n.
ADDRESS
CK#
DM
DQ
CK
CK#
DM
DQ
CK
WRITE
Bank,
Col b
WRITE
T0
Bank,
Col b
T0
WL ±
t
WL = 2
CCD
NOP
WL = 2
T1
NOP
T1
t
DQSS
WL ± t DQSS
T1n
52
WRITE
Bank,
Col n
T2
DI
b
NOP
T2
DI
b
T2n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
WL = 2
NOP
WRITE
6
Bank,
T3
Col n
6
T3
512Mb: x4, x8, x16 DDR2 SDRAM
DON’T CARE
DON’T CARE
T3n
T3n
WL = 2
NOP
6
T4
DI
NOP
n
T4
TRANSITIONING DATA
TRANSITIONING DATA
T4n
T4n
t
t
DQSS.
DQSS.
©2004 Micron Technology, Inc. All rights reserved.
NOP
6
6
T5
T5
NOP
DI
n
T5n
T5n
NOP
NOP
6
T6
T6
WRITEs
T6n

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