pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 91

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Figure 3-34 SCAN Timer Generation
The 40...60 MHz SYSCLK is divided by 32 to obtain a cell clock CellClk.
The Tnow counter with 24-bit width increments by 2**TStepC every CellClk. The value
of this counter is made available as relative time reference to other blocks. Parameter
TStepC is set in
The absolute time bases are provided by dividing the CellClk first by 256 and then by a
programmable divider of 7 bit (1...127).
Timer ms125count is derived from bit 4 of the programmable divider.
Timer ms10count is derived by from bit 7 of the programmable divider.
The divider is programmed with the parameter SCANP found in register
on Page 286
Table 3-35
Default value is SCANP=63, for the frequency of 51.84 MHz, which is easy to obtain as
1/3 of 155.52 MHz, the SDH/Sonet frequency.
The following scan is performed:
Data Sheet
Frequency [MHz]
40
51.84
SYSCLK
40 ..52 MHz
depending on the SYSCLK value:
Timer Values for Clock Generation
Register 63 "USCONF/DSCONF" on Page
Divider
/32
SCANP
49
63
CellClk * 2**TstepC
Divider
/256
91
period of ms10count
[s]
0.010035
0.009956
Programmble
Divider
Tnow
24 bit
1.25ms
246.
Period
Functional Description
Period
10ms
PXF 4333 V1.1
delta [%]
0.35
0.44
ms125count
ms10count
“ERCCONF0”
VBR
8bit
8bit
2001-12-17
ABM-3G