pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 313

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

VCMerge
INITRAM
INITSDRAM
CORE
WGS
Data Sheet
VC Merge Enable
This bit enables VC-Merge operation on a global basis. It
determines the usage (required width) of the Cell Pointer RAM,
since VC-Merge operation requires one additional flag ‘EOP Mark’
in the CPR.
(see also
Page
0
1
Init RAM
Start of Initialization of the internal RAM.
This bit is automatically cleared after execution.
1
(0)
Init SDRAM
Initialization and configuration of the external SDRAM. This bit must
be set to 1 after reset (initial pause of at least 200 µs is necessary)
and is automatically cleared by the ABM-3G after configuration of
the SDRAM has been executed.
1
(0)
Downstream Core Disable
This bit disables the downstream ABM-3G Core, which is necessary
in some MiniSwitch configurations (Uni-Directional Mode using one
core).
It is recommended to set CORE = 0 in Bi-directional operation
modes.
1
0
Work Group Switch Mode
Selects MiniSwitch (Uni-directional) Mode if set to 1.
139)
Table 5-10 "SSRAM Configuration Examples" on
VC-Merge operation disabled.
VC-Merge operation enabled.
Starts internal RAM initialization procedure.
Note: The internal RAM initialization process can be
self-clearing
Starts SDRAM initialization procedure
self-clearing
Downstream ABM-3G core disabled
Downstream ABM-3G core enabled
activated only once after hardware reset.
313
Register Description
PXF 4333 V1.1
2001-12-17
ABM-3G