pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 217

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Register 39 QCT2
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
MGconf/DQsch
Data Sheet
MGconf/
DQsch
15
7
Queue Configuration Transfer Register 2
14
Merge Group Configured/
Dummy Queue Scheduled
The meaning of this flag depends on bit ’RSall’:
RSall=’0’
The queue is not configured as a ’dummy queue’ and may be
configured as a VC-merge group member:
MGconf
0
1
RSall=’1’
The queue is configured as a ’dummy queue’:
DQsch
6
Read/Write
0000
QCT2
Written by CPU to configure VC-Merge operation
H
13
5
The queue is neither a dummy queue, nor member of a
VC-merge group.
The queue is member of a VC-merge group. The VC-
merge group is determined by bit field ’MGID(6:0).
Note: To disable an active VC-merge group, bit
44
’QIDvalid’ must be reset. Deactivating the queue
by setting QIDvalid=’0’ automatically starts an
internal process to delete the queue from the VC-
merge group. In response to resetting ’QIDvalid’
the ABM-3G will generate an interrupt (Bit
’UQVCMGD/DQVCMGD’ in Register 103: ISRC)
and reset bit ’MGconf/DQsch’ in this table.
H
12
4
MinBG(7:0)
217
MGID(6:0)
11
3
10
2
Register Description
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0