pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 267

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Internal Table 9: Scheduler Configuration Table Fractional Transfer Registers
The Scheduler Configuration Table Fractional Transfer Registers are used to access the
internal Upstream/Downstream Scheduler Configuration Tables Fractional Part (SCTF)
containing 128 entries each.
Table 7-22
Table 7-23
SCTFU and SCTFD are transfer registers for one 16-bit SCTF upstream/downstream
table entry. The upstream and downstream Scheduler Blocks use different tables
(internal RAM) addressed via the MAR. The Scheduler Block number representing the
table entry which needs to be read or written must be written to the
Register). The dedicated SCTFU/D table entry is read into the SCTFU/D registers or
modified by the SCTFU/D register value with a write mechanism. The associated mask
registers, SMSKU and SMSKD, allow a bit-wise Write operation (0 - unmasked, 1 -
masked). In case of Read operation, the dedicated SCTFU/D register bit will be
overwritten by the respective SCTFU/D table entry bit value. In case of Write operation,
the dedicated SCTFU/D register bit will modify the value of the respective SCTFU/D
table entry bit.
Data Sheet
15
15
15
15
15
15
SCTF RAM Entry
SCTF RAM Entry
(Downstream)
(Upstream)
USCTFM
DSCTFM
USCTFT
DSCTFT
Registers SCTF Upstream Table Access
Registers SCTF Downstream Table Access
0
0
0
0
0
0
Table 7-22
and
267
Table 7-23
15
15
15
15
WAR (0..127
WAR (0..127
Entry Select:
Entry Select:
RAM Select:
RAM Select:
MAR=1F
MAR=17
summarize the registers.
H
H
Register Description
D
D
WAR
)
)
0
0
0
0
PXF 4333 V1.1
(Word Address
2001-12-17
ABM-3G