pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 297

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
7.2.25
Register 101 ISRU
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
BCFGE
QIDINV
BUFER1
LCIINVAL
PARITYER
Data Sheet
Unused
BUFER
15
7
3
Interrupt Status/Mask Registers
Interrupt Status Register Upstream
CDVOV MUXOV
BCFGE
14
Buffer Configuration Error upstream
This interrupt is generated if the ABM-3G tries to write a cell into a
disabled queue. The cell is discarded in this case.
(Typically occurs on queue configuration errors.)
Unexpected buffer error number 1. Should never occur in normal
operation. Immediate reset of the chip recommended.
Error when performing the internal address reduction
The cell is discarded.
Parity error at UTOPIA Receive Upstream (PHY) Interface
detected.
6
Read/Write
0000
ISRU
Read by CPU to evaluate interrupt events related to the
upstream core. Interrupt indications must be cleared by writing
a 1 to the respective bit locations; writing a 0 has no effect;
H
QIDINV
13
5
BUFER
E3
AAL5
COL
12
H
1
4
297
RMCER BIP8ER
INVAL
LCI
11
3
PARITY
ER
10
2
Register Description
SOCER
BUFER
PXF 4333 V1.1
9
1
4
2001-12-17
ABM-3G
BUFER
reserve
8
2
0
d

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