pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 195

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
Table 7-6
63
7.2.9
Internal Table 2: Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3
The Traffic Class Table Transfer Registers are used to access the internal Traffic Class
Table (TCT) containing 2*16 entries of 4*64 bits each (16 traffic classes per ABM-3G
core, 4 words of 64 bits per entry).
involved.
TCT0, TCT1, TCT2 and TCT3 are the transfer registers used to access the 4*64 bit TCT
table entries.
Core selection, traffic class number, and 64-bit word selection of the table entry which
needs to be read or written must be programmed to the Word Address Register (WAR).
The dedicated TCT table entry 64-bit word is read into the TCT3/TCT2/TCT1/TCT0
registers or modified by the TCT3/TCT2/TCT1/TCT0 register values with a write
mechanism. The associated Mask Registers MASKi (i=3..0) allow a bit-wise masking for
Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated
TCTi (i=3..0) register bit will be overwritten by the respective TCT table entry bit value.
In case of Write operation, the dedicated TCTi (i=3..0) register bit will modify the
respective TCT table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
TCT table bit field MAR(4:0) must be set to 1. Bit 5 of MAR starts the transfer and is
automatically cleared after execution.
Data Sheet
15
15
MASK3
TCT3
Traffic Class Table Transfer Registers
0 15
0 15
Registers for TCT Table Access
MASK2
TCT2
TCT RAM entry
0 15
0 15
MASK1
TCT1
Table 7-6
195
0 15
0 15
shows an overview of the registers
MASK0
TCT0
0
0
0
Register Description
15
15
TCT entry select:
WAR (0..127
PXF 4333 V1.1
RAM select:
MAR=01
2001-12-17
ABM-3G
H
D
)
0
0

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