pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 179

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Register 18 UMIC/DMIC
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
UMIC(17:2)
DMIC(17:2)
Data Sheet
15
7
Upstream/Downstream Minimum Occupation Capture Registers
14
Upstream Minimum Occupation Capture Counter
Downstream Minimum Occupation Capture Counter
These bit fields represent the most significant 16 bits of the internal
18-bit wide counters reflecting the absolute minimum number of
cells stored in the respective external cell buffer since the last Read
access (minimum cell filling level within measurement interval).
The CPU determines the minimum number of cells with a
granularity of 4 by reading register UMIC/DMIC and left shifting the
value by 2:
min_level(17:0):= (xMIC(17:2) << 2)
The counter value is automatically cleared to 0000
Note: The reset value is modified by chip logic immediately after
6
Read only, self-clearing on Read
FFFF
(modified by chip logic immediately after reset)
UMIC
Read by CPU
reset or clearing read and thus shall not be included in
register reset value test programs.
H
13
5
28
UMIC/DMIC(17:10)
UMIC/DMIC(9:2)
H
12
4
179
DMIC
11
3
10
2
29
Register Description
H
PXF 4333 V1.1
H
9
1
after Read.
2001-12-17
ABM-3G
8
0