pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 53

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

3.2.5.2
The DPLL features two factors programmed by parameters m and n in register
“PLL1CONF” on Page 287
Figure 3-8
The division factor determined by m must be chosen such that intermediate frequency
f
The multiplication factor determined by n must be chosen such that intermediate
frequency f
Finally, one or two divisions by the two factors (f
to achieve the final clock frequency.
When choosing the factors m and n, two conditions must be met:
• n=1..24: f
• f
3.2.5.3
The following numbers are assumed for this example:
• ABM-3G internal core clock: 52 MHz
Data Sheet
1
Register PLL1CONF
Lockedi Div2Eni Div1Eni Bypassi
is in the range 2..15 MHz based on the input frequency at signal ‘SYSCLK’.
15
n=25..63: f
2
f
in
must be in a range of 100 to 200 MHz
X
2
DPLL Programming
Programming Example
(0)
1
is twice or four times the final value in case of DPLL1.
(1)
must be in a range of 5..15 MHz
1
DPLL Structure
must be in a range of 2..6 MHz
(m + 1)
1
PUi
f
1
RESi
=
:
2..15 MHz
f
in
f
⁄
1
(
m
+
1
Mi(3:0)
)
(n + 1)
53
;
f
2
1
=
,f
2
f
) may be enabled in case of DPLL1
f
2
in
×
X
(0)
--------------
m
(1)
n
+
+
1
1/2
1
Functional Description
Ni(5:0)
X
(0)
(1)
PXF 4333 V1.1
1/2
2001-12-17
ABM-3G
0
f
out