pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 116

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Definition of Necessary Traffic Classes
The ABM-3G allows up to 16 traffic classes to be defined by Traffic Class Table RAM
entry via the registers
classes:
• CBR (real-time) = traffic class 1
• GFR (non-real-time) = traffic class 2
• UBR (non-real-time) = traffic class 3
Assignment of the Queues to the Traffic Classes
Each queue must relate to a defined traffic class according to the Queue Configuration
Table RAM entry via the TCID(3:0) bits of the QCT table.
Assignment of the Queues (QIDs) to the Scheduler Blocks (SBIDs)
Every Scheduler Block (SB) possesses a certain number of queues depending on the
assignment by the user of the SBID(5:0) bits of register
ample, every ADSL device has four data connections so that four queues per SB are
necessary. Each SB of the ABM-3G has one real-time queue and an arbitrary number of
non-real-time queues. For SB 0..254, indicate that the first queue belongs to Traffic
Class 1, the 2nd and 3rd Queue to Traffic Class 2, and the 4th Queue to Traffic Class 3.
There are 1020 (1..1020) queues altogether for SB 0..254. The 256th SB must be able
to serve the 255 xDSL devices (255 SBs and appropriate queues). Thus, SB 255 has
255 x 2 = 510 non-real-time queues as every SB from 0..254 possesses two GFR non-
real-time queues (GFR has a guaranteed minimum rate; thus, each GFR queue needs
a per VC queueing). The 255 UBR queues of SBs 0..254 need only one UBR queue at
the 256th SB as UBR has no guaranteed minimum rate. As every SB has only one real-
time queue, the 255 real-time queues from SBs 0..254 flow into the one real-time queue
of SB 255. Therefore, SB 256 needs the assignment of 510 (GFR) + 1 (UBR) + 1 (CBR)
= 512 queues.
4.2.4
In normal operation, no microprocessor interaction is necessary as the ABM-3G chip
does all queueing and scheduling automatically. For maintenance purposes, periodically
the microprocessor could read out the counters for buffer overflow events. Some over-
flow events may also be programmed as interrupts.
4.2.5
Due to the WFQ Scheduler concept of the ABM-3G, the Connection Acceptance Check
(CAC) is very simple:
• Check if the Guaranteed Rate of the connection fits within the spare bandwidth of the
Data Sheet
Scheduler.
Normal Operation
Bandwidth Reservation
TCT0
to
TCT3
(see
Page
116
198f). In this example, there are 3 traffic
“QCT1” on Page
Operational Description
PXF 4333 V1.1
214. In the ex-
2001-12-17
ABM-3G