pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 143

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

7
This chapter provides both an overview of the ATM Buffer Manager ABM-3G Register
Set and detailed register descriptions and Table Access descriptions.
7.1
Control and operation of the ABM-3G chip can be done by directly configuring Status
Registers or, to a large extent, by programming the internal tables. Access to these
tables is not direct, but occurs via Transfer Registers and Transfer Commands. Any
transfer must be prepared by writing appropriate values to the Transfer Registers. Bit
positions named ’don’t Write’ must be masked by writing 1 to the corresponding bit
positions in the Mask Register. This avoids overwriting these table bit positions with the
Transfer Register contents, which may cause fatal malfunction. The specific table
position which should be modified with the Transfer Register contents is selected via
Register WAR. Transfer is started by writing the table address to Register MAR and also
setting the ’Start’ bit. The ABM-3G device will reset the ’Start’ bit after transfer
completion.
The ABM-3G contains the following internal tables for configuration:
• LCI Table (LCI)
• Traffic Class Table (TCT)
• Queue Configuration Table (QCT)
• Queue Parameter Table 1 (QPT1)
• Queue Parameter Table 2 (QPT2)
• Scheduler Block Occupancy Table (SBOC)
• Scheduler Block Rate Tables (consisting of 4 tables):
• Merge Group Table (MGT)
• VBR Table (AVT)
Figure 7-1
mask registers:
Data Sheet
- SCTI Upstream
- SCTI Downstream
- SCTF Upstream
- SCTF Downstream
Register Description
Overview of the ABM-3G Register Set
gives an overview of all (user accessible) tables and related control/transfer/
143
Register Description
PXF 4333 V1.1
2001-12-17
ABM-3G