pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 54

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

• Clock supply: 52 MHz at signal SYSCLK
In this example, signal SYSCLKSEL must be connected to V
core clock to the DPLL1 output. (Please refer to
DPLL1 Programming
A reasonable value for parameter M1 in register
which results in
f
Now a possible value for parameter N1 is N1 = 25 which results in
f
To achieve the 52 MHz core clock division factor 1 shall be enabled.
Thus, for this example the value 3B19
The conditions given above are met because f
(n=25) and f
Note: Multiple combinations of parameters are possible to achieve a 52 MHz clock in
3.2.5.4
After power-on reset, the DPLL is in bypass mode which means that signal ‘SYSCLK’ is
directly feeding the internal core clock. After basic configuration of at least the DPLL
configuration registers, the bypass can be disabled which will make a glitch-free
adjustment of the internal clocks to the selected frequency.
3.2.6
The ABM-3G provides three different reset sources, as shown in
hardware signal RESET affects the entire device. The self-clearing software reset bit
‘SWRES’ in register
Hardware reset as well as software reset bit ‘SWRES’ completely initialize the device
into power-on reset state.
Data Sheet
1
2
= 52 MHz / (12 + 1) = 4 MHz.
= 4 MHz * (25 + 1) = 104 MHz.
this example.
Initialization Phase
Reset System
2
=104 MHz is between 100 and 200 MHz.
“MODE1” on Page 312
H
must be programmed to register PLL1CONF.
54
also affects the entire device.
“PLL1CONF” on Page 287
Figure
1
=4 MHz is in the range of 2..6 MHz
3-7)
SS
Functional Description
to connect the internal
PXF 4333 V1.1
Figure
is M1 = 12
2001-12-17
ABM-3G
3-9. The