pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 62

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

ABM-3G
PXF 4333 V1.1
Functional Description
Under normal operation conditions, once a cell is accepted by the CAA, it will be emitted
at a time. The only reason for cell discard after cell acceptance is queue disabling. The
cell itself is stored in the external cell store RAM. The logical queue is a linked list of
pointers to the cell store RAM providing a FIFO ordering.
3.4.1.2
Logical Buffer Views
The ABM-3G Cell Buffer is structured by the Buffer Manager into the following major
logical views:
• Global Buffer,
• Logical Queues,
• Scheduler Blocks,
• Traffic Classes.
Each view is characterized by attributes, state variables (e.g. occupancy counters), and
programmable thresholds.
3.4.1.2.1 Global Buffer
A total amount of 262,140 cells can be stored per direction in the global cell buffer.
Depending on the particular threshold configuration, global buffer space can be
exclusively reserved or shared among different logical queues, scheduler blocks or
traffic classes and the individual connections assigned to them.
3.4.1.2.2 Logical Queues
The concept of logical queues is implemented to provide isolation between connections
or groups of connections sharing the global buffer. Strict per VC queueing is achieved
by exclusively assigning connections to logical queues. However, it is also possible to
assign more than one connection to a particular logical queue.
A total of 8192 logical queues is provided per direction, with QIDs ranging from 0 to 8191.
QID 0 is reserved for the common real-time (CRT) bypass queue. It may be used for real-
time traffic in case of an unstructured ABM-3G output, as e.g. in input buffered switches
and also for cascading multiple ABM-3Gs. The common real-time bypass is
programmed as a rate limited queue.
Section 3.4.2.1
provides scheduling related
details.
3.4.1.2.3 Scheduler Blocks
From a buffer manager perspective, Scheduler Blocks (SB) can be conceived as a
grouping of logical queues sharing the bandwidth provided by the configured SB rate.
Each logical queue, except the common real-time (CRT) bypass (QID=0), is
unambiguously assigned to a scheduler block.
A total of 128 Scheduler Blocks is provided per direction.
Data Sheet
62
2001-12-17