pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 351

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
8.4.5
Timing of the Synchronous Dynamic RAM (SDRAM) Interface is simplified as all signals
are referenced to the rising edge of RAMCLK. In
signals output by the ABM-3G have identical delay times with reference to the clock.
When reading from RAM, the ABM-3G samples the data within a window at the rising
clock edge.
Figure 8-9
Data Sheet
Table 8-14
No.
110
110A
111
112
113
CSRDATi(31:0), output
CSRRASi, CSRCASi,
CSRDATi(31:0), input
CSRBAi0, CSRBAi1
CSRCSi, CSRWEi,
Parameter
T
F
Setup time
CSRADRi(13:0), CSRCSi, CSRRASi, CSRCASi,
CSRWEi, CSRBAi0, CSRBAi1 before RAMCLK
rising
Hold time
CSRADRi(13:0), CSRCSi, CSRRASi, CSRCASi,
CSRWEi, CSRBAi0, CSRBAi1 after RAMCLK
rising
Delay CSRDATi Output after RAMCLK rising
CSRADRi(13:0),
RAMCLK
RAMCLK
CSR SDRAM Interface(s)
Generic SDRAM Interface Timing Diagram
SDRAM Interface AC Timing Characteristics
RAMCLK
: Period RAMCLK
: Frequency RAMCLK
351
Figure
111
114
110
Min
2.5
1.5
19.2
3
8-9, it can be seen that all
Electrical Characteristics
112
113
115
Limit Values
Typ
PXF 4333 V1.1
Max
52
6.5
2001-12-17
ABM-3G
Unit
ns
MHz
ns
ns
ns

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