pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 211

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

7.2.10
Internal Table 3: Queue Configuration Table Transfer Registers QCT0..6
Queue Configuration Table Transfer Registers are used to access the internal Queue
Configuration Table (QCT) containing 2*8192 entries. The lower 8K entries control the
upstream core queues and the upper 8K entries control the downstream core queues.
Table 7-8
entry 0 (common real time bypass)
Table 7-8
111
QCT0...QCT6 are the transfer registers for one 112 bit QCT table entry. The core
selection and queue number representing the table entry which needs to be read or
written must be written to the Word Address Register (WAR). The dedicated QCT table
entry is read into the QCT0..QCT6 registers or modified by the QCT0..QCT6 register
values with a write mechanism. The associated Mask Registers MASK0..MASK6 allow
a bit-wise Write operation (0 - unmasked, 1 - masked). In case of Read operation, the
dedicated QCT0..QCT6 register bit will be overwritten by the respective QCT table entry
bit value. In case of Write operation, the dedicated QCT0..QCT6 register bit will modify
the respective QCT table entry bit value.
Note: It is recommended not to Write to bit fields (111:64) and (15:0) of the QCT table
The 13 LSBs (= Bit 12..0) of the WAR register select the queue-specific entry that will be
accessed and bit ’CoreSel’ the ABM-3G core.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
QCT table, bit field MAR(4:0) must be set to 2. Bit 5 of MAR starts the transfer and is
automatically cleared after execution.
Data Sheet
15
15
=FFFF
MASK6
QCT6
entries; i.e. registers MASK0, MASK6, MASK5, MASK4 and MASK3 should
always be programmed with FFFF
0 15
0 15
H
shows an overview of the registers involved. Some fields are not used for
Queue Configuration Table Transfer Registers
=FFFF
MASK5
QCT5
Registers for Queue Configuration Table Access
0 15
0 15
H
=FFFF
MASK4
QCT4
QCT RAM entry
0 15
0 15
H
=FFFF
MASK3
QCT3
0 15
0 15
H
H
.
211
MASK2
QCT2
0 15
0 15
MASK1
QCT1
0 15
0 15
=FFFF
MASK0
Register Description
QCT0
PXF 4333 V1.1
0
0
0
H
15
15
(0..16383
MAR=02
2001-12-17
ABM-3G
Queue
select:
select:
WAR
RAM
0
0
H
D
)