pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 230

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

7.2.12
Internal Table 5: Merge Group Table Transfer Registers MGT0..MGT2
The Merge Group Table Transfer Registers are used to access the internal Merge Group
Table (MGT) containing 2*128 entries of 48 bit each.
the registers involved.
Table 7-12
47
MGT0..MGT2 are the transfer registers for one 48-bit MGT table entry. The Scheduler
Block number representing the table entry which needs to be read or written must be
written to the Word Address Register (WAR). The dedicated MGT table entry is read into
the MGT0..MGT2 Registers or modified by the MGT0..MGT2 register values with a write
mechanism. The associated Mask Registers MASK0..MASK2 allow a bit-wise Write
operation (0 - unmasked, 1 - masked). In case of read operation, the dedicated
MGT0..MGT2 register bit will be overwritten by the respective MGT table entry bit value.
In case of Write operation, the dedicated MGT0..MGT2 register bit will modify the
respective MGT table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to
select the MGT table, bit field MAR(4:0) must be set to 6. Bit 5 of MAR starts the transfer
and is automatically cleared after execution.
Data Sheet
15
15
MASK2
MGT2
Merge Group Table Transfer Registers
Registers for MGT Table Access
0 15
0 15
MGT RAM entry
MASK1
MGT1
0 15
0 15
230
MASK0
MGT0
0
0
0
Table 7-10
Register Description
shows an overview of
15
15
PXF 4333 V1.1
WAR (0..255
RAM Select:
Entry select:
MAR=07
2001-12-17
ABM-3G
H
D
0
0
)