pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 173

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

RXS
WAIT
SP
SAB
SE
Data Sheet
Note: Status bits SP, SAB, SE are used for transmit, the others for receive.
Receive Packet Start
A ‘1’ indicates that the first octets of a new packet are available in
registers UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and
DA5RXDAT1 respectively.
Wait
A ‘1’ indicates that no valid octets are available in registers
UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and DA5RXDAT1
respectively. Read access to any read register while WAIT is asserted
results into an error interrupt.
Segmentation Pending
A ‘1’ indicates that a cell is ready to be transmitted towards the
ABM-3G core. A cell is ready either when 48 octets have been written
to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and DA5TXDAT1
respectively or when the last cell is being built.
Bit ‘SP’ is set when the 48-byte transmit buffer is full and it is reset as
soon as at least 4-octet space is available for new octets. The
microprocessor has to poll this bit before writing the next 48-octet
bunch or beginning a new packet. If the microprocessor attempts to
write to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and
DA5TXDAT1 respectively while ‘SP’ is set, an interrupt is generated
and the write access is delayed by the READY signal.
Segmentation Abort
A ‘1’ indicates that the transmission of a packet has been aborted
because the enable bit EN was reset by the microprocessor before the
transmission was completed. The AAL5 unit automatically closed the
packet with an abort sequence in the last cell (length field set to 0).
Note: Status bit ‘SE’ is not set in this case.
Segmentation Ended
A ‘1’ indicates that the transmission of a packet has been completed
successfully.
173
Register Description
PXF 4333 V1.1
2001-12-17
ABM-3G