XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 83

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

User I/Os by Bank
Table 69
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
Dual-Purpose I/O.
Table 69: User I/Os Per Bank for XC3S200A in the FG320 Package
Table 70: User I/Os Per Bank for XC3S400A in the FG320 Package
Footprint Migration Differences
Table 71
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.
Table 71: FG320 Footprint Migration Differences
DS529-4 (v1.5) July 10, 2007
Product Specification
Top
Right
Bottom
Left
Top
Right
Bottom
Left
E13
P14
Pin
N7
Package
Package
TOTAL
Legend:
TOTAL
Edge
Edge
DIFFERENCES
and
summarizes any footprint and functionality
Bank
R
0
2
2
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Table 70
N.C.
N.C.
N.C.
I/O Bank
I/O Bank
XC3S200A
0
1
2
3
0
1
2
3
indicate how the available user-I/O
Table 71
Maximum I/O
Maximum I/O
Migration
unconditionally migrate
3
248
251
60
64
60
64
61
64
62
64
INPUT
INPUT
INPUT/VREF
XC3S400A
101
101
I/O
I/O
35
19
38
35
19
38
9
9
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INPUT
INPUT
11
10
13
40
12
10
13
42
6
7
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
52
30
21
30
21
52
1
0
1
0
VREF
VREF
23
24
5
7
6
5
5
7
7
5
Pinout Descriptions
CLK
CLK
32
32
8
8
8
8
8
8
8
8
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