XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 69

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
DS529-4 (v1.5) July 10, 2007
Product Specification
42
2
3
0
IO_L04N_3/VREF_3 11
IO_L05P_3/LHCLK0
IO_L05N_3/LHCLK1
IO_L06P_3/LHCLK2
IO_L06N_3/LHCLK3
IO_L07P_3/LHCLK4
IO_L08P_3/LHCLK6
IO_L07N_3/LHCLK5
IO_L08N_3/LHCLK7
IP_L13N_3/VREF_3 35
I/O: Unrestricted, general-purpose
user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated configuration
pins, SUSPEND pin
N.C.: Not connected
IO_L02N_3
IO_L01N_3
IO_L03N_3
IO_L09P_3 24
IO_L09N_3 25
IO_L10N_3 29
IO_L11N_3 30
IO_L12N_3 32
IO_L02P_3
IO_L01P_3
IO_L03P_3
IO_L04P_3 10
IO_L10P_3 27
IO_L11P_3 28
IO_L12P_3 31
IP_L13P_3 33
R
VCCAUX 36
VCCO_3 14
VCCO_3 23
VCCINT
GND
GND
GND
GND
TMS
TDI
12
13
15
16
17
18
19
20
21
22
26
34
1
2
3
4
5
6
7
8
9
X
Figure 17: TQ144 Package Footprint (top view)
26
30
13
4
DUAL: Configuration, AWAKE
pins, then possible user I/O
CLK: User I/O, input, or global
buffer input
JTAG: Dedicated JTAG port pins
GND: Ground
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Bank 0
Bank 2
8
8
4
4
VREF: User I/O or input voltage
reference for bank
VCCO: Output voltage supply for
bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply voltage
108 VCCAUX
107
106
105 IO_L11N_1
104 IO_L10N_1
103 IO_L11P_1
102 IO_L10P_1
101 IO_L09N_1
100
99 IO_L09P_1
98 IO_L08N_1
97 IP_1/VREF_1
96 IO_L08P_1
95 VCCO_1
94
93
92
91
90
89
88
87
86 VCCO_1
85
84 IO_L03N_1
83
82 IO_L03P_1
81
80 IP_1/VREF_1
79 IO_1
78 IO_L01N_1/LDC2
77 IO_L02N_1/LDC0
76 IO_L01P_1/HDC
75 IO_L02P_1/LDC1
74 SUSPEND
73 DONE
Pinout Descriptions
TDO
GND
GND
VCCINT
IO_L07N_1/RHCLK7
IO_L06N_1/RHCLK5
IO_L07P_1/RHCLK6
IO_L06P_1/RHCLK4
GND
IO_L05N_1/RHCLK3
IO_L05P_1/RHCLK2
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
GND
DS529-4_10_031207
69