XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 70

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3A FPGAs, including the
XC3S50A, the XC3S200A, and the XC3S400A.
Table 62
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S50A, the XC3S200A, and the XC3S400A FPGAs.
The XC3S50A has 51 unconnected balls, indicated as N.C.
(No Connection) in
black diamond character ( ) in
provides the common footprint for the XC3S200A and
XC3S400A.
Table 62
different assignments between the XC3S50A and the
XC3S200A/XC3S400A, highlighted in light blue. See
"Footprint Migration Differences," page 83
information.
All other balls have nearly identical functionality on all three
devices.
footprint migration differences for the FT256 package.
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration
mode.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
Pinout Table
Table 62: Spartan-3A FT256 Pinout
70
Bank
0
0
0
0
0
0
0
0
0
0
0
0
Table 65
lists all the package pins. They are sorted by bank
also indicates that some differential I/O pairs have
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/
VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
N.C. (◆)
IP_0
N.C. (◆)
N.C. (◆)
http://www.xilinx.com/bvdocs/publications/s3a_pin.zip
XC3S50A
summarizes the Spartan-3A FPGA
Table 62
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/
VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/
VREF_0
IO_L06P_0
and
XC3S200A
XC3S400A
Table
Figure 18
62.
Figure 19
for additional
and with the
FT256
Ball
C13
D13
B14
B15
D11
C12
A13
A14
A12
B12
E10
D10
VREF
VREF
Type
www.xilinx.com
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
.
Table 62: Spartan-3A FT256 Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/
GCLK5
IO_L09P_0/
GCLK4
IO_L10N_0/
GCLK7
IO_L10P_0/
GCLK6
IO_L11N_0/
GCLK9
IO_L11P_0/
GCLK8
IO_L12N_0/
GCLK11
IO_L12P_0/
GCLK10
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/
PUDC_B
IO_L20P_0/
VREF_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0/VREF_0
XC3S50A
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/
GCLK5
IO_L09P_0/
GCLK4
IO_L10N_0/
GCLK7
IO_L10P_0/
GCLK6
IO_L11N_0/
GCLK9
IO_L11P_0/
GCLK8
IO_L12N_0/
GCLK11
IO_L12P_0/
GCLK10
IO_L13N_0
IO_L13P_0
IO_L14N_0/
VREF_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/
PUDC_B
IO_L20P_0/
VREF_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0/VREF_0
XC3S200A
XC3S400A
DS529-4 (v1.5) July 10, 2007
Product Specification
FT256
Ball
C11
C10
D12
A11
A10
B10
F10
D9
C9
D8
C8
C7
C6
D7
C5
D5
C4
D6
A9
B8
A8
A7
E7
F8
B6
A6
A5
B4
A4
B3
A3
E6
F7
F9
E9
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
VREF
VREF
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R