XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 41

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Table 30: CLB Distributed RAM Switching Characteristics
Table 31: CLB Shift Register Switching Characteristics
DS529-3 (v1.5) July 10, 2007
Product Specification
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
T
WPH
WPH
Symbol
Symbol
T
T
T
AH,
T
SHCKO
SRLDH
SRLDS
T
T
T
T
REG
WS
DS
AS
DH
, T
, T
T
WH
WPL
WPL
R
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data appearing on
the shift register output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
Minimum High or Low pulse width at CLK input
Description
Description
www.xilinx.com
–
0.18
0.30
0.13
0.01
0.88
0.13
0.16
0.90
Min
Min
0.07
-5
-5
DC and Switching Characteristics
Max
1.69
Max
4.11
–
–
–
–
–
–
–
–
–
–
0.36
0.59
0.13
0.01
1.01
0.18
0.16
1.01
Min
Min
0.02
-4
-4
Max
2.01
Max
4.82
–
–
–
–
–
–
–
–
–
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41