XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 52

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
Table 44: Power-On Timing and the Beginning of Configuration
52
Notes:
1.
2.
3.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, and BPI modes.
(2)
(3)
Symbol
Notes:
1.
2.
3.
V
CCAUX
(Open-Drain)
CCO
The V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
PROG_B
V
(Supply)
(Supply)
(Supply)
(Output)
V
Bank 2
CCAUX
lines.
(Input)
INIT_B
CCINT
CCLK
CCINT
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
, V
Figure 11: Waveforms for Power-On and the Beginning of Configuration
CCAUX
, and V
CCO
supplies can be applied in any order.
Description
1.0V
2.0V
1.0V
CCINT
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T
T
POR
PROG
, V
CCAUX
, and V
T
Table
PL
CCO
8. This means power must be applied to all V
All
All
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
All
All
T
Device
ICCK
All Speed Grades
Min
250
0.5
0.5
–
–
–
–
–
–
DS529-3 (v1.5) July 10, 2007
Product Specification
DS529-3_01_112906
Max
0.5
0.5
18
1
2
2
–
4
-
1.2V
3.3V
2.5V
or
CCINT
Units
ms
ms
ms
ms
ms
ms
, V
μs
ns
μs
CCO
,
R