XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 28

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Output Propagation Times
Table 23: Timing for the IOB Output Path
28
Notes:
1.
2.
Clock-to-Output Times
Propagation Times
Set/Reset Times
T
Symbol
The numbers in this table are tested using the methodology presented in
Table 8
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
T
T
T
T
IOGSRQ
IOCKP
IOOLP
IOSRP
IOOP
and
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
The time it takes for data to travel from
the IOB’s O input to the Output pin
The time it takes for data to travel from
the O input through the OFF latch to
the Output pin
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
11.
Description
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
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Conditions
(2)
(2)
(2)
, 12 mA output
, 12 mA output
, 12 mA output
Table 26
Table
25.
and are based on the operating conditions set forth in
Device
All
All
All
DS529-3 (v1.5) July 10, 2007
Max
2.87
2.78
2.70
3.63
8.62
Speed Grade
-5
Product Specification
Max
3.13
2.91
2.85
3.89
9.65
-4
Units
ns
ns
ns
ns
ns
R