XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 74

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Pinout Descriptions
User I/Os by Bank
Table 63
pins are distributed between the four I/O banks on the
FT256 package.
The XC3S50A FPGA in the FT256 package has 51
unconnected balls, labeled with an “N.C.” type. These pins
are also indicated in
as a Dual-Purpose I/O.
Table 63: User I/Os Per Bank on XC3S50A in the FT256 Package
Table 64: User I/Os Per Bank on XC3S200A and XC3S400A in the FT256 Package
74
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Edge
Edge
and
Table 64
I/O Bank
I/O Bank
Figure
0
1
2
3
0
1
2
3
indicate how the available user-I/O
18. The AWAKE pin is counted
Maximum I/O
Maximum I/O
144
195
40
32
40
32
47
50
48
50
I/O
I/O
21
12
15
53
27
11
30
69
5
1
www.xilinx.com
INPUT
INPUT
20
21
7
5
2
6
6
6
2
7
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
21
26
30
21
52
1
4
0
1
0
DS529-4 (v1.5) July 10, 2007
VREF
VREF
15
21
3
3
6
3
5
5
6
5
Product Specification
CLK
CLK
30
32
8
8
6
8
8
8
8
8
R