XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 39

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Table 28: Recommended Number of Simultaneously
Switching Outputs per V
Notes:
1.
2.
3.
DS529-3 (v1.5) July 10, 2007
Product Specification
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V
limits for the respective I/O standard.
If more than one signal standard is assigned to the I/Os of a
given bank, refer to XAPP689: Managing Ground Bounce in
Large FPGAs for information on how to perform weighted
average SSO calculations.
Signal Standard
(IOSTANDARD)
R
CCO
Bottom
(Banks
Top,
0,2)
8
8
1
8
8
8
–
–
6
–
4
3
–
5
–
3
2
-GND Pair (V
8
8
8
8
TQ144
(Banks
Package Type
Right
Left,
1,3)
–
–
1
–
–
Input Only
Input Only
–
–
–
–
–
5
3
6
2
4
6
1
5
3
4
3
Bottom
CCAUX
FG400, FG484,
FT256, FG320,
(Banks
Top,
0,2)
22
27
22
27
22
27
27
22
27
IL
4
–
–
8
–
5
3
–
9
–
4
3
/V
FG676
IH
=3.3V)
voltage
(Banks
Right
Left,
1,3)
10
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–
–
4
–
–
–
–
–
–
–
4
8
2
4
7
1
9
4
5
3
DC and Switching Characteristics
39