XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 57

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Serial Peripheral Interface (SPI) Configuration Timing
Table 51: Timing for Serial Peripheral Interface (SPI) Configuration Mode
DS529-3 (v1.5) July 10, 2007
Product Specification
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
PUDC_B
VS[2:0]
CSO_B
Symbol
INIT_B
M[2:0]
CCLK
(Input)
(Input)
(Input)
(Input)
(Input)
MOSI
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
R
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
MOSI output valid delay after CCLK falling clock edge
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
T
MINIT
Figure 14: Waveforms for Serial Peripheral Interface (SPI) Configuration
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
<1:1:1>
<0:0:1>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
CCO
www.xilinx.com
T
DSU
T
MCCL1
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
DC and Switching Characteristics
50
0
T
T
(see
(see
New ConfigRate active
CCLK1
See
See
See
MCCL n
Data
T
T
V
Maximum
DCC
Table
Table
Table 49
Table 49
Table 49
–
–
45)
45)
Data
DS529-3_06_102506
T
T
CCLK n
T
CCD
MCCH n
Units
Data
ns
ns
57