XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 49

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Phase Shifter (PS)
Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 40: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
DS529-3 (v1.5) July 10, 2007
Product Specification
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
PSCLK
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
)
Symbol
R
(2)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Description
Description
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Table
CLKIN < 60 MHz
CLKIN
36.
≥
Table 8
60 MHz
and
40%
Min
1
±[INTEGER(10 • (T
±[INTEGER(15 • (T
Table
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
DC and Switching Characteristics
-5
39.
Phase Shift Amount
Max
60%
Speed Grade
167
±[MAX_STEPS •
±[MAX_STEPS •
40%
Min
CLKIN
CLKIN
1
-4
– 3 ns))]
– 3 ns))]
Max
60%
167
Units
steps
MHz
Units
ns
ns
-
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