XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 43

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

18 x 18 Embedded Multiplier Timing
Table 33: 18 x 18 Embedded Multiplier Timing
DS529-3 (v1.5) July 10, 2007
Product Specification
Notes:
1.
2.
3.
4.
Combinatorial Delay
T
Clock-to-Output Times
T
T
T
Setup Times
T
T
T
Hold Times
T
T
T
Clock Frequency
F
MULT
MSCKP_P
MSCKP_A
MSCKP_B
MSDCK_P
MSDCK_A
MSDCK_B
MSCKD_P
MSCKD_A
MSCKD_B
MULT
Symbol
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
R
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)
Data setup time at the A input before the active transition at the CLK
when using the AREG input register
Data setup time at the B input before the active transition at the CLK
when using the BREG input register
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)
Data hold time at the A input after the active transition at the CLK
when using the AREG input register
Data hold time at the B input after the active transition at the CLK
when using the BREG input register
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register
(2,3)
(1)
(2,4)
(3)
(3)
Description
(4)
(4)
(4)
(4)
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3.56
0.00
0.00
0.00
0.35
0.35
Min
–
–
–
0
-5
DC and Switching Characteristics
Max
4.36
0.84
4.44
280
Speed Grade
–
–
–
–
–
–
3.98
0.00
0.00
0.00
0.45
0.45
Min
–
–
–
0
-4
Max
4.88
1.30
4.97
250
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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