XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 24

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
24
Notes:
1.
2.
3.
4.
Setup Times
Hold Times
The numbers in this table are tested using the methodology presented in
Table 8
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s
active edge.
DCM output jitter is included in all measurements.
Symbol
T
T
T
T
PSDCM
PHDCM
PSFD
PHFD
and
Table
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition at
the Global Clock pin. The DCM is
not in use. The Input Delay is
programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in use.
The Input Delay is programmed.
11.
Description
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 5,
without DCM
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 5,
without DCM
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Conditions
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Table 26
and are based on the operating conditions set forth in
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Table
Table
Device
22. If this is true of the data Input, add the
22. If this is true of the data Input, subtract
-0.36
-0.52
-0.33
-0.17
-0.07
-0.63
-0.56
-0.42
-0.80
-0.69
2.45
2.59
2.38
2.38
1.91
2.55
2.32
2.21
2.28
2.33
Min
-5
DS529-3 (v1.5) July 10, 2007
Speed Grade
Product Specification
-0.36
-0.52
-0.29
-0.12
-0.58
-0.56
-0.42
-0.75
-0.69
2.68
2.84
2.68
2.57
2.17
2.76
2.76
2.60
2.63
2.41
0.00
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R