XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 61

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 55: Timing for the JTAG Test Access Port
DS529-3 (v1.5) July 10, 2007
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
T
T
F
Symbol
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
CCHDNA
CCLDNA
TCK
The numbers in this table are based on the operating conditions set forth in
TCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
The time from the falling transition on the TCK pin to data appearing at the TDO pin
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
R
T
TDITCK
T
TMSTCK
Figure 16: JTAG Waveforms
All operations on XC3S50A, XC3S200A, and
All devices and functions except those shown below
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700A and XC3S1400A FPGAs
All functions except those shown below
Configuration commands (CFG_IN, ISC_PROGRAM)
All functions except ISC_DNA command
During ISC_DNA command
XC3S400A FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
All operations on XC3S700A and XC3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
Description
www.xilinx.com
T
TCKTDI
T
TCKTMS
Table
8.
T
TCKTDO
T
CCH
DC and Switching Characteristics
1/F
TCK
T
CCL
11.0
Min
1.0
7.0
7.0
2.0
10
10
0
0
5
5
0
All Speed
Grades
DS099_06_040703
10,000
10,000
Max
11.0
33
20
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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