XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 23

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
DS529-3 (v1.5) July 10, 2007
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
The numbers in this table are tested using the methodology presented in
Table 8
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
Symbol
ICKOFDCM
T
ICKOF
and
R
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
11.
Table
Description
22. If the latter is true, add the appropriate Output adjustment from
LVCMOS25
output drive, Fast slew
rate, with DCM
LVCMOS25
output drive, Fast slew
rate, without DCM
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Conditions
(2)
(2)
, 12mA
, 12mA
(3)
Table 26
and are based on the operating conditions set forth in
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Device
Table
DC and Switching Characteristics
25.
Max
3.18
3.21
2.97
3.39
3.51
4.59
4.88
4.68
4.97
5.06
-5
Speed Grade
Max
3.42
3.27
3.33
3.50
3.99
5.02
5.24
5.12
5.34
5.69
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23