XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 79

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320,
supports two Spartan-3A FPGAs, the XC3S200A and the
XC3S400A, as shown in
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 68
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The shaded rows indicate pinout differences between the
XC3S200A and the XC3S400A FPGAs. The XC3S200A
has three unconnected balls, indicated as N.C. (No
Connection) in
character ( ) in
All other balls have nearly identical functionality on all three
devices.
footprint migration differences for the FG320 package.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
Pinout Table
Table 68: Spartan-3A FG320 Pinout
DS529-4 (v1.5) July 10, 2007
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 71
lists all the package pins. They are sorted by bank
http://www.xilinx.com/bvdocs/publications/s3a_pin.zip
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/VREF_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
R
Table 68
Table 68
summarizes the Spartan-3A FPGA
Pin Name
and with the black diamond
Table 68
and
Figure
and
20.
Figure
FG320
Ball
C15
C16
A16
B16
A14
A15
C14
B15
D12
C13
A13
B13
B12
C12
E11
A11
B11
D10
C11
B10
F11
C9
20.
GCLK
GCLK
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
.
Table 68: Spartan-3A FG320 Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L13N_0/GCLK9
IO_L13P_0/GCLK8
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0/VREF_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0/PUDC_B
IO_L24P_0/VREF_0
IP_0
IP_0
IP_0
XC3S400A: IP_0
XC3S200A: N.C. (◆)
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
Pin Name
Pinout Descriptions
FG320
G11
Ball
A10
D13
D14
E12
E13
F10
F12
E10
B14
D11
T17
R16
G7
G8
G9
B9
B7
A8
C8
B8
C7
D8
E9
D9
B6
A6
A4
A5
E7
D6
C6
A3
B4
D5
C5
A2
B3
E5
E6
B5
E8
F8
F7
F9
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
VREF
VREF
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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