XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 17

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
DS529-3 (v1.5) July 10, 2007
Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
IOSTANDARD
Attribute
(3)
(3)
(3)
(3)
(3)
(3)
R
24
16
24
12
16
12
8
4
6
12
16
24
12
16
12
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
(4)
2
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(mA)
Conditions
I
12
16
24
12
16
24
12
16
24
12
16
12
OL
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
Test
(mA)
–12
–16
–24
–12
–16
–24
–12
–16
–24
–12
–16
–12
I
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
OH
0.25 • V
Max (V)
0.45
V
0.4
0.4
0.4
0.4
Characteristics
OL
Logic Level
CCO
V
0.75 • V
V
V
V
CCO
CCO
CCO
CCO
Min (V)
V
2.4
OH
–
–
–
–
www.xilinx.com
0.45
CCO
0.4
0.4
0.4
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards (Continued)
Notes:
1.
2.
3.
4.
5.
PCI33_3
PCI66_3
PCIX
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
IOSTANDARD
The numbers in this table are based on the conditions set forth in
V
For the LVCMOS and LVTTL standards: the same V
These higher-drive output standards are supported only on
Table 8
Descriptions of the symbols used in this table are as follows:
I
I
V
V
V
V
V
V
limits apply for both the Fast and Slow slew attributes.
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
Tested according to the relevant PCI specifications.
OL
OH
OL
OH
IL
IH
CCO
REF
TT
Attribute
–
–
–
–
(4)
–
–
–
(5)
(5)
(4)
–
(4)
the output current condition under which V
the input voltage that indicates a Low logic level
–
the output current condition under which V
the input voltage that indicates a High logic level
the output voltage that indicates a Low logic level
the voltage applied to a resistor termination
the output voltage that indicates a High logic level
(4)
the reference voltage for setting the input switching threshold
and
the supply voltage for output drivers
(4)
Table
11.
(mA)
Conditions
13.4 –13.4 V
16.2 –16.2
DC and Switching Characteristics
I
1.5
1.5
1.5
6.7
8.1
24
16
24
16
OL
8
8
8
Test
(mA)
–0.5
–0.5
–0.5
–6.7
–8.1
–16
–16
I
–8
–8
–8
–8
–8
OH
V
10% V
10% V
10% V
V
V
V
V
TT
TT
Max (V)
TT
TT
TT
TT
V
– 0.475 V
– 0.475 V
0.4
0.4
0.4
0.4
0.4
Characteristics
– 0.61
– 0.80
OL
– 0.6
– 0.8
Logic Level
CCO
CCO
CCO
OL
OH
is tested
is tested
90% V
90% V
90% V
V
V
V
V
V
V
V
OL
V
V
TT
TT
Min (V)
CCO
CCO
CCO
CCO
CCO
TT
TT
TT
TT
and V
V
+ 0.475
+ 0.475
+ 0.61
+ 0.80
OH
+ 0.6
+ 0.8
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
CCO
CCO
CCO
OH
17