XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 3

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DS529-1 (v1.4.1) July 10, 2007
Introduction
The Spartan™-3A family of Field-Programmable Gate
Arrays (FPGAs) solves the design challenges in most
high-volume,
applications. The five-member family offers densities ranging
from 50,000 to 1.4 million system gates, as shown in
The Spartan-3A family builds on the success of the earlier
Spartan-3E and Spartan-3 FPGA families by increasing the
amount of I/O per logic, significantly reducing the cost per
I/O. New features improve system performance and reduce
the cost of configuration. These Spartan-3A family
enhancements, combined with proven 90 nm process
technology, deliver more functionality and bandwidth per
dollar than ever before, setting the new standard in the
programmable logic industry.
Because of their exceptionally low cost, Spartan-3A FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking,
display/projection, and digital television equipment.
The Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost,
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
•
•
•
•
Table 1: Summary of Spartan-3A FPGA Attributes
Notes:
1.
DS529-1 (v1.4.1) July 10, 2007
Product Specification
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A 1400K
Device
Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
Dual-range V
Suspend, Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
♦
♦
♦
By convention, one Kb is equivalent to 1,024 bits.
© 2006-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
System
200K
400K
700K
Gates
50K
cost-sensitive,
CCAUX
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Logic Cells
Equivalent
supply simplifies 3.3V-only design
13,248
25,344
1,584
4,032
8,064
R
Rows Columns
I/O-intensive
16
32
40
48
72
<
B
L
B
(One CLB = Four Slices)
12
16
24
32
40
CLB Array
1,472 5,888
2,816 11,264
electronic
CLBs
Total
176
448
896
Table
www.xilinx.com
Introduction and Ordering Information
1,792
3,584
1.
Slices
Total
704
•
•
•
•
•
•
•
•
Distributed
RAM bits
176K
♦
♦
♦
♦
♦
♦
♦
♦
Abundant, flexible logic resources
♦
♦
♦
♦
♦
Hierarchical SelectRAM™ memory architecture
♦
♦
Up to eight Digital Clock Managers (DCMs)
♦
♦
♦
♦
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
♦
♦
♦
♦
♦
Complete Xilinx ISE™ and WebPACK™ development
system software support plus
MicroBlaze™ and PicoBlaze™ embedded processor cores
Low-cost QFP and BGA packaging, Pb-free options
♦
♦
♦
11K
28K
56K
92K
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 333 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI
support
Densities up to 25,344 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Up to 576 Kbits of fast block RAM with byte write enables
for processor applications
Up to 176 Kbits of efficient distributed RAM
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Common footprints support easy density migration
Compatible with select
Compatible with higher density
(1)
288K
360K
360K
576K
Block
bits
Spartan-3A FPGA Family:
RAM
54K
(1)
Multipliers DCMs
Dedicated
Platform Flash
16
20
20
32
3
Spartan-3AN
2
4
4
8
8
Spartan-3A Starter Kit
with JTAG
Product Specification
Spartan-3A DSP
Maximum
User I/O
144
248
311
372
502
nonvolatile FPGAs
®
technology
Differential
Maximum
I/O Pairs
112
142
165
227
FPGAs
64
3