XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 100

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XC3S50A

Manufacturer Part Number
XC3S50A
Description
Spartan-3a Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

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Pinout Descriptions
User I/Os by Bank
Table 75
distributed between the four I/O banks on the FG484
Table 75: User I/Os Per Bank for the XC3S700A in the FG484 Package
Table 76: User I/Os Per Bank for the XC3S1400A in the FG484 Package
100
Top
Right
Bottom
Left
Top
Right
Bottom
Left
Package
Package
TOTAL
TOTAL
Edge
Edge
and
Table 76
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
indicate how the user-I/O pins are
Maximum I/O
Maximum I/O
372
375
92
94
92
94
92
94
95
94
194
195
I/O
I/O
58
33
42
61
58
33
43
61
www.xilinx.com
package. The AWAKE pin is counted as a Dual-Purpose
I/O.
INPUT
INPUT
17
15
12
17
61
17
15
13
17
62
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
30
21
52
30
21
52
1
0
1
0
DS529-4 (v1.5) July 10, 2007
VREF
VREF
33
10
34
8
8
9
8
8
8
8
Product Specification
CLK
CLK
32
32
8
8
8
8
8
8
8
8
R

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