XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 50

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Miscellaneous DCM Timing
Table 41: Miscellaneous DCM Timing
DNA Port Timing
Table 42: DNA_PORT Interface Timing
50
Notes:
1.
Notes:
1.
2.
3.
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
T
T
T
T
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
T
T
T
Symbol
T
T
T
DNADCKO
DNACLKH
DNACLKF
DNACLKL
DNADSU
DNARSU
DNASSU
DNADH
DNARH
DNASH
Symbol
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
CLK High time
CLK Low time
(2)
(3)
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
configuration successfully completed (DONE pin goes High)
and clocks applied to DCM DLL
™
-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
Description
www.xilinx.com
Description
CCINT
applied to FPGA
μs
.
Min
1.0
0.5
1.0
0.5
5.0
0.5
1.0
1.0
0
0
Min
N/A
N/A
N/A
N/A
3
DS529-3 (v1.5) July 10, 2007
10,000
Product Specification
Max
100
1.5
–
–
–
–
–
∞
∞
Max
N/A
N/A
N/A
N/A
–
seconds
seconds
minutes
minutes
Units
CLKIN
MHz
cycles
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
R