XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 55

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Master Serial and Slave Serial Mode Timing
Table 49: Timing for the Master Serial and Slave Serial Configuration Modes
DS529-3 (v1.5) July 10, 2007
Product Specification
Notes:
1.
2.
(Input/Output)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
(Open-Drain)
CCO
DCC
CCD
CCH
CCL
CCSER
Symbol
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
DOUT
CCLK
DIN
R
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the
CCLK input pin
Figure 12: Waveforms for Master Serial and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
www.xilinx.com
T
CCD
Bit 1
Table
8.
T
T
Master
Master
Master
Master
Slave/
MCCL
SCCL
Slave
Slave
Slave
Slave
Both
Both
DC and Switching Characteristics
Bit n
1/F
CCSER
T
CCO
Bit n-64
Bit n+1
All Speed Grades
Min
1.5
1.0
T
T
7
0
0
0
MCCH
SCCH
See
See
See
See
Bit n-63
Table 47
Table 48
Table 47
Table 48
Max
100
100
10
–
–
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
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