XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 25

no-image

XC3S50A

Manufacturer Part Number
XC3S50A
Description
Spartan-3a Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S50A
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S50A-4FT256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50A-4FT256C
Manufacturer:
XILINX
0
Part Number:
XC3S50A-4FT256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50A-4FT256I
Manufacturer:
XILINX
0
Part Number:
XC3S50A-4FTG256C
Manufacturer:
MOSEL
Quantity:
3
Part Number:
XC3S50A-4FTG256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50A-4FTG256C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
XC3S50A-4FTG256C
Quantity:
1 080
Part Number:
XC3S50A-4FTG256I
Manufacturer:
XILINX
Quantity:
152
Part Number:
XC3S50A-4TQG100C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
DS529-3 (v1.5) July 10, 2007
Product Specification
Notes:
1.
2.
3.
Setup Times
T
T
Hold Times
T
T
Set/Reset Pulse Width
T
IOPICK
IOPICKD
IOICKP
IOICKPD
RPW_IOB
Symbol
The numbers in this table are tested using the methodology presented in
Table 8
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
and
R
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Minimum pulse width to SR control
input on IOB
Table
11.
Description
Table
Table
22.
22. When the hold time is negative, it is possible to change the data before the clock’s active
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
www.xilinx.com
Conditions
(2
(2)
(2)
(2)
Table 26
and are based on the operating conditions set forth in
DELAY_
VALUE
IFD_
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
DC and Switching Characteristics
Device
All
All
All
All
All
–1.04
–1.85
–2.59
–3.01
–3.37
–3.38
–3.77
–4.09
–4.45
1.24
1.98
2.93
3.73
4.28
4.11
5.04
5.87
6.42
1.33
Min
Speed Grade
-5
–1.03
–1.85
–2.59
–2.99
–3.34
–3.34
–3.69
–4.00
–4.28
1.91
2.36
3.10
3.98
4.57
4.40
5.45
6.36
6.99
1.61
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25

Related parts for XC3S50A