XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 60

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash
60
Notes:
1.
2.
3.
T
(t
T
(t
T
(t
T
(t
ACC
CE
ELQV
OE
GLQV
AVQV
BYTE
FLQV,
Symbol
These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
)
)
)
t
FHQV
)
Parallel NOR Flash PROM chip-select time
Parallel NOR Flash PROM output-enable time
Parallel NOR Flash PROM read access time
For x8/x16 PROMs only: BYTE# to output valid time
Description
www.xilinx.com
(3)
T
ACC
≤
T
CCLKn min
T
T
T
BYTE
CE
OE
Requirement
(
≤
≤
≤
T
T
)
T
INITADDR
INITADDR
–
INITADDR
T
CCO
DS529-3 (v1.5) July 10, 2007
–
T
DCC
Product Specification
–
PCB
Units
ns
ns
ns
ns
R