XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 22

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document are designated as Preview, Advance,
Preliminary, or Production, as shown in
category is defined as follows:
Preview: These specifications are based on estimates only
and should not be used for timing analysis.
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx
ISE™ software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
22
Table
16. Each
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Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A FPGA speed files (v1.37), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for
these files are shown in
precise, and worst-case data, use the values reported by
the Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 16: Spartan-3A v1.37 Speed Grade Designations
Table 17
FPGA speed files.
Table 17: Spartan-3A Speed File Version History
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Version
1.37
1.36
1.35
1.34
Device
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provides the recent history of the Spartan-3A
available via
ISE 9.2.01i
ISE 9.1.03i
previously
AR24992
AR24992
Release
ISE 9.2i;
Answer
Record
Answer
Record
ISE
Preview
Updated pin-to-pin setup and hold
times
adjustment
setup/hold times
RAM clock width
XC3S400A, all speed grades and all
temperature grades, upgraded to
Production
XC3S50A, XC3S200A, XC3S700A,
XC3S1400A, all speed grades and all
temperature grades, upgraded to
Production.
XC3S700A and XC3S1400A -4 speed
grade upgraded to Production. Updated
pin-to-pin timing numbers.
Table
Advance
(Table
16. For more complete, more
DS529-3 (v1.5) July 10, 2007
(Table
19), TMDS output
Description
Preliminary
Product Specification
(Table
(Table
25) multiplier
33), and block
34).
Production
–
–
–
–
–
4,
4,
4,
4,
4,
–
–
–
–
–
5
5
5
5
5
R