M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 99

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
9.2 Interrupts and Interrupt Vector
e
E
1
. v
J
Figure 9.2 Interrupt Vector
Table 9.1 Fixed Vector Tables
NOTE:
6
0
________
_______
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2 shows the interrupt vector.
9.2.1 Fixed Vector Tables
Interrupt source
Undefined instruction FFFDC
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Oscillation stop and
low voltage detection
DBC
NMI
Reset
re-oscillation detection,
1
C
9
1 .
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
B
The fixed vector tables are allocated to the addresses from FFFDC
fixed vector tables. In the flash memory version of MCU, the vector addresses (H) of fixed vectors are
used by the ID code check function. For details, refer to the section "flash memory rewrite disabling
function".
2 /
0
2
9
1
M
0
G
(1)
(2)
1
r a
0 -
o r
3 .
1
u
, 0
1
p
2
(1)
2
0
0
7
page 73
Address (L) to address (H)
Vector table addresses
FFFEC
FFFE8
FFFFC
FFFE0
FFFE4
FFFF8
FFFF0
FFFF4
Vector address (H)
Vector address (L)
f o
16
16
16
16
16
16
16
16
16
4
to FFFEB
to FFFFB
to FFFE3
to FFFE7
to FFFF3
to FFFF7
5
to FFFDF
to FFFEF
to FFFFF
8
16
16
16
16
16
16
16
16
16
MSB
If the contents of address
FFFE7
ecution starts from the address
shown by the vector in the
relocatable vector table
Interrupt on UND instruction
Interrupt on INTO instruction
0 0 0 0
0 0 0 0
16
Low address
Mid address
is FF
Remarks
16
High address
, program ex-
0 0 0 0
16
to FFFFF
LSB
_______
M16C/60, M16C/20
serise software
maual
Address match interrupt
Watchdog timer,
clock generating circuit,
voltage detection circuit
NMI interrupt
Reset
16
. Table 9.1 lists the
Reference