M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 229

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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1
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Figure 14.25 STSPSEL Bit Functions
Table 14.14 STSPSEL Bit Functions
6
0
Function
Output of SCL2 and SDA2 pins
1
9
C
Start/stop condition interrupt
request generation timing
1 .
B
2 /
0
14.1.3.3 Arbitration
2
9
1
Unmatching of the transmit data and SDA
edge of SCL
U2RB register is updated. If the ABC bit is set to 0 (updated bitwise), the ABT bit is set to 1 at the same
time unmatching is detected during check, and is cleared to 0 when not detected. In cases when the
ABC bit is set to 1, if unmatching is detected even once during check, the ABT bit is set to 1
(unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to 0 (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to 1 (SDA
occur, in which case the SDA
is set to 1 (unmatching detected).
M
0
G
1
r a
0 -
o r
3 .
1
u
(1) In slave mode,
STPSEL bit
SCL2
SDA2
(2) In master mode,
STPSEL bit
SCL2
SDA2
, 0
1
p
2
2
CKDIR is set to 1 (external clock)
CKDIR is set to 0 (internal clock), CKPH is set to 1(clock delayed)
0
0
7
2
. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
Set STAREQ
to 1 (start)
page 203
0
Start condition detection
interrupt
Set to 1 by
program
f o
4
5
2
8
pin is placed in the high-impedance state at the same time the ABT bit
STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are detec-
ted
Start condition detection
interrupt
1st
Set to 0 by
program
2nd
1st
3rd
2nd
2
4th
pin input data is checked synchronously with the rising
3rd
5th
4th
6th 7th
2
5th
output stop enabled) causes arbitration-lost to
6th
Set STPREQ
to 1 (start)
8th
7th
9th bit
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
are completed
8th
Start/stop condition generation
Stop condition detection
interrupt
Set to 1 by
program
9th bit
Stop condition detection
interrupt
Set to 0 by
program